Silicon Validation Engineer, Memory Subsystem, Silicon
Skills
- Silicon Validation
- DDRPHY
- DRAM
- Memory Controller
- Emulation
- Post-Silicon Bringup
- Lab Automation
- Scripting
- C
- Python
- FPGA
About the role
About the job:
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities:
Work with Architecture, Design and product teams to understand requirements for memory subsystem validation (e.g., double data rate physical layer (DDRPHY), Memory Controller, dynamic random-access memory (DRAM)).
Understand the design and develop/execute validation tests to establish functionality of new design on emulation platform for tapeout for DDRPHY and DRAM subsystem.
Drive the post silicon bringup and validation activities for the DDRPHY/DRAM interface including its tuning and characterization.
Develop various post silicon validation/debug/margin tools related to DDRPHY and DRAM.
Provide regular updates about Emulation/Silicon health to platform, software and volume manufacturing teams.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience in silicon validation.
Experience with DDRPHY and DRAM tuning and characterization over PVT.
Experience in developing test and debug infrastructure (e.g., software tools, lab equipment) and test/lab automation scripting.
Experience with low power DRAM interface protocols and compliance.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Familiarity with Prototyping platforms like Emulators or Field Programmable Gate Array (FPGAs).
Familiarity with power or performance measurement of SoCs.
C/Python Coding experience.
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